1. Field of the Invention
The present invention is directed to solid state fabrication techniques and, more particularly, to techniques used to produce three-dimensional, doped films particularly useful in the construction of solid state memory devices.
2. Description of the Background
Memory cells, such as those of dynamic random access memories (DRAM), are comprised of two main components: a field-effect transistor (FET) and a capacitor. In memory cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the FET. Wordlines are generally etched from a polysilicon-1 layer. A doped region of silicon substrate functions as the lower (storage-node) capacitor plate while a doped polysilicon-2 layer generally functions as the upper capacitor plate (cell plate). Although planar capacitors have generally proven adequate for use in memory chips up to the one-megabyte level, they are considered to be unusable for more advanced memory generations.
As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which can be collected by the lower capacitor plate. The phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a xe2x80x9csoftxe2x80x9d error. Secondly, the sense amplifier differential signal is reduced. That aggravates noise sensitivity and makes it more difficult to design column sense-amplifiers having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the smaller charge stored within the cell leaks to an unusable level sooner, which necessitates more frequent interruptions for refresh overhead.
As a result of the problems associated with the use of planar capacitors for high-density memories, manufacturers of, for example, 4-megabyte DRAMs are utilizing cell designs based on non-planar capacitors. Two basic non-planar capacitor designs are currently in use: the trench capacitor and the stacked capacitor. Both types of non-planar capacitors typically require a considerably greater number of masking, deposition, and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally in a planar capacitor. Because trench capacitors are fabricated in trenches which are etched in the substrate, some trench capacitor structures can be susceptible to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage caused by the parasitic transistor effect between adjacent trenches. Another problem is cell storage node-to-substrate leakage attributable to single crystal defects which are induced by stress associated with the trench structure. Yet another problem is the difficulty of completely cleaning the trenches during the fabrication process. Failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. However, in the stacked capacitor design, the layer of material which forms the storage node is in contact with the substrate. Subsequent processing steps tend to cause outdiffusion of the dopant which adversely affects the diode junction profile as well as the threshold voltage for the access transistor. Thus, the need exists for a method of controlling the outdiffusion from a doped three-dimensional film.
The present invention, in its broadest aspect, is directed to a solid state fabrication technique for controlling the amount of outdiffusion from a three-dimensional film. The technique is comprised of the steps of providing a first layer of insitu doped film in a manner to define an upper and a lower portion. A second layer of undoped film is then provided in a manner to similarly define an upper and a lower portion. The first and second layers are etched according to a predetermined pattern. The second layer is doped with an implant to obtain a desired dopant density which decreases from the upper to the lower portion of the second layer. By decreasing the density of the desired dopant at the lower portion of the film, outdiffusion of the dopant into the substrate is greatly reduced. Outdiffusion of the dopant from the upper portion of the second layer results in the dopant migrating to the lower portion of the second layer. Thus, outdiffusion into the substrate, and the problems caused thereby, are eliminated or greatly reduced.
In one application of the present invention, the fabrication technique may be used for controlling the amount of outdiffusion from a stacked, polysilicon storage node. According to that embodiment of the present invention, a first layer of insitu doped polysilicon is provided in a manner to define an upper portion and a lower portion of the first layer. A second layer of undoped polysilicon is provided in a manner to define an upper and a lower portion of the second layer. The first and second layers of polysilicon are etched according to a storage node pattern. The second layer of polysilicon is doped with an angled implant to obtain a desired dopant density which decreases from the upper portion to the lower portion of the second layer. The doping step may be carried out using two different angles of orientation for the implant. The angle of incidence of the implant with the wafer""s surface varies from between approximately seven to twenty-five degrees. The lower dopant dosages coupled with improved performance of the capacitor offset the extra fabrication time required by the two-angle implant.
The method of the present invention can be adapted to provide a fabrication technique for constructing a stacked capacitor. The present invention is accordingly directed to a fabrication technique for constructing a stacked capacitor and such a stacked capacitor. The fabrication technique for constructing the stacked capacitor is comprised of the steps of providing a first layer of insitu, lightly doped film. A second layer of undoped film is provided on top of the first layer. The first and second layers are etched according to a storage node pattern. The second layer is doped to achieve a higher level of dopant in the second layer than the level of dopant in the first layer. A level of dielectric material is provided and then etched so as to leave portions of the dielectric layer on top of the second layer. A layer of cell plate material is provided and then etched to form the capacitor""s cell plate. By utilizing a two film approach for creating the capacitor""s storage node, outdiffusion from the storage node into the substrate is greatly reduced or eliminated. Controlling or eliminating the outdiffusion results in improved characteristics of the diode junction profile, longer periods before static refresh is required, and better results with respect to soft errors. Those, and other advantages and benefits of the present invention, will become apparent from the Description Of The Preferred Embodiments hereinbelow.